1. Field of the Invention
The present invention relates to a technology for power control on a semiconductor integrated circuit including a plurality of computing units.
2. Description of the Related Art
With high integration of semiconductor integrated circuits in recent years, the number of IP cores (computing units) to be mounted on a single semiconductor integrated circuit is increasing, and structures and control methods for those IP cores are becoming more complex and diversified. Furthermore, more and more IP cores may be mounted on a system-on-chip (a system LSI) in the future. Therefore, the demand for effective power management of a plurality of IP cores is growing.
Due to the above situation, “Geovanni D Micilli, Luca Benini, “Networks on Chips: a new SoC paradigm” IEEE Computer, January 2002, Pages: 70 to 78” discloses a technology for performing asynchronous communication using a communication protocol shared by IP cores mounted on a system LSI to simplify control on the IP cores and improve reusability of the IP cores. Furthermore, JP-A 2006-237189 (KOKAI) discloses a technology for providing a power control circuit that performs power control on each of IP cores individually, so that power of an IP core that has transmitted an interrupt signal indicating process completion notification can be individually turned off.
However, the technology disclosed in the literature by Geovanni et al. includes only a method for simplifying a structure by enabling each IP core on a system LSI to operate independent of other IP cores, and does not include any methods for reducing power consumption. Therefore, it is difficult to effectively perform power management of IP cores. Furthermore, in the technology disclosed in JP-A 2006-237189 (KOKAI), all IP cores are integrally managed. Therefore, if load on the power control circuit increases due to increase of the number of the IP cores, it takes longer time to perform power control. Thus, power control may not be effectively performed.